A bipolar junction transistor usually includes two back-to-back p-n junctions that share a thin common region. In other words, a bipolar junction transistor typically includes three regions, two outer regions commonly known as “emitter” and “collector” respectively, and a middle region commonly known as “base”. Electrical connections are generally made to all three regions.
A heterojunction bipolar transistor (HBT) is a bipolar junction transistor that employs at least two different kinds of semiconductor materials. By virtue of this difference in material, energy band-gaps, as well as other material related properties, may be made different for regions of emitter, base and collector of the HBT. In addition, a gradual change of semiconductor material, also known as grading, may also be possible inside one or more of the regions. The use of heterojunction provides an added degree of freedom in design, which often results in improved performance, when being compared with its homojunction counterpart, of the HBT device.
Improvement in transistor performance, especially its operation speed, is generally considered as essential for achieving improved performance of a network communication system wherein various types of transistors are normally used. Bipolar transistors with a silicon germanium (“SiGe”) intrinsic base may be capable of delivering performance required for such communication system. So far, a SiGe-HBT has demonstrated cut-off frequency of up to 350 GHz (fT). SiGe is a compound semiconductor with a band-gap narrower than pure silicon (Si). Similar to a conventional silicon (“Si”) bipolar transistor except for the base, SiGe is normally used as a base material inside a SiGe-HBT.
On the other hand, collector resistance also heavily influences the maximum operating frequency (fmax). As other parameters of a HBT improve, parasitic resistance (Rc) of the collector of HBT is increasingly becoming a limiting factor for the device performance. High collector parasitic resistance Rc may limit cut-off frequency fT, the impact of which may be measured, as is well known in the art, as a function of base transit time and collector space-charge transit time. A lowered fT may ultimately limit the maximum operating frequency fmax of the HBT device.
Collector parasitic resistance, Rc, may be considered coming mainly from three sources: a first resistance as the electrons flow vertically through the lightly doped semiconductor region from a collector-base junction down to a buried layer (“sub-collector”), a second resistance as the electrons flow laterally through the heavily doped semiconductor called the buried layer, and a third resistance as the electrons flow vertically from the buried layer through the heavily doped semiconductor region called the reach-through up the surface silicide region. The doped semiconductor regions are usually formed by ion implantation followed by thermal anneal, or by dopant diffusion, or in-situe doped deposition as known in the art.
As described above, there is a need in the art to reduce the overall collector parasitic resistance Rc in order to improve the performance of a HBT device, in particular its operating speed. This may be accomplished by reducing resistances from one or more of the above three sources.